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MC9S08PT16 MC9S08PT16 series support: MC9S08PT16 and mc9s08pt8 features ? 8-bit s08 central processor unit (cpu) C up to 20 mhz bus at 2.7 v to 5.5 v across temperature range of -40 c to 105 c C supporting up to 40 interrupt/reset sources C supporting up to four-level nested interrupt C on-chip memory C up to 16 kb flash read/program/erase over full operating voltage and temperature C up to 256 byte eeprom; 2-byte erase sector; program and erase while executing flash C up to 2048 byte random-access memory (ram) C flash and ram access protection ? power-saving modes C one low-power stop mode; reduced power wait mode C peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode ? clocks C oscillator (xosc) - loop-controlled pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 39.0625 khz or 4 mhz to 20 mhz C internal clock source (ics) - containing a frequency- locked-loop (fll) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 c to 70 c and 2% deviation across temperature range of -40 c to 105 c; up to 20 mhz ? system protection C watchdog with independent clock source C low-voltage detection with reset or interrupt; selectable trip points C illegal opcode detection with reset C illegal address detection with reset ? development support C single-wire background debug interface C breakpoint capability to allow three breakpoints setting during in-circuit debugging C on-chip in-circuit emulator (ice) debug module containing two comparators and nine trigger modes ? peripherals C acmp - one analog comparator with both positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering C adc - 12-channel, 12-bit resolution; 2.5 s conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger C crc - programmable cyclic redundancy check module C ftm - two flex timer modulators modules including one 6-channel and one 2-channel ones; 16-bit counter; each channel can be configured for input capture, output compare, edge- or center-aligned pwm mode C iic - one inter-integrated circuit module; up to 400 kbps; multi-master operation; programmable slave address; supporting broadcast mode and 10-bit addressing C mtim - one modulo timer with 8-bit prescaler and overflow interrupt C rtc - 16-bit real timer counter (rtc) C sci - two serial communication interface (sci/ uart) modules optional 13-bit break; full duplex non-return to zero (nrz); lin extension support C spi - one 8-bit serial peripheral interface (spi) modules; full-duplex or single-wire bidirectional; master or slave mode C tsi - supporting up to 16 external electrodes; configurable software or hardware scan trigger; fully support freescale touch sensing software library; capability to wake mcu from stop3 mode freescale semiconductor document number: MC9S08PT16 data sheet: technical data rev. 1, 7/4/2012 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2011C2012 freescale semiconductor, inc.
? input/output C 37 gpios including one output-only pin C one 8-bit keyboard interrupt module (kbi) C two true open-drain output pins C four, ultra-high current sink pins supporting 20 ma source/sink current ? package options C 44-pin lqfp C 32-pin lqfp C 20-pin soic; 20-pin tssop C 16-pin tssop MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 2 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 4 1.1 determining valid orderable parts...................................... 4 2 part identification ...................................................................... 4 2.1 description......................................................................... 4 2.2 format ............................................................................... 4 2.3 fields ................................................................................. 4 2.4 example ............................................................................ 5 3 parameter classification ........................................................... 5 4 ratings ...................................................................................... 5 4.1 thermal handling ratings ................................................... 5 4.2 moisture handling ratings .................................................. 6 4.3 esd handling ratings ......................................................... 6 4.4 voltage and current operating ratings ............................... 6 5 general ..................................................................................... 7 5.1 nonswitching electrical specifications ............................... 7 5.1.1 dc characteristics ................................................. 7 5.1.2 supply current characteristics ............................... 12 5.1.3 emc performance ................................................. 13 5.2 switching specifications..................................................... 13 5.2.1 control timing ........................................................ 13 5.2.2 debug trace timing specifications ......................... 15 5.2.3 ftm module timing ............................................... 15 5.3 thermal specifications ....................................................... 16 5.3.1 thermal characteristics ......................................... 16 6 peripheral operating requirements and behaviors .................... 18 6.1 external oscillator (xosc) and ics characteristics........... 18 6.2 nvm specifications ............................................................ 19 6.3 analog ............................................................................... 21 6.3.1 adc characteristics............................................... 21 6.3.2 analog comparator (acmp) electricals ................. 23 6.4 communication interfaces ................................................. 24 6.4.1 spi switching specifications .................................. 24 6.5 human-machine interfaces (hmi)...................................... 27 6.5.1 tsi electrical specifications ................................... 27 7 dimensions ............................................................................... 27 7.1 obtaining package dimensions ......................................... 27 8 pinout ........................................................................................ 28 8.1 signal multiplexing and pin assignments........................... 28 8.2 device pin assignment ...................................................... 30 9 revision history ......................................................................... 32 MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 3
ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: pt16 and pt8. part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: mc 9 s08 pt aa b cc 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values mc qualification status ? mc = fully qualified, general market flow 9 memory ? 9 = flash based s08 core ? s08 = 8-bit cpu pt device family ? pt aa approximate flash size in kb ? 16 = 16 kb ? 8 = 8 kb b temperature range (c) ? v = C40 to 105 table continues on the next page... 1 2 ordering parts MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 4 freescale semiconductor, inc.
field description values cc package designator ? ld = 44-lqfp ? lc = 32-lqfp ? tj = 20-tssop ? wj = 20-soic ? tg = 16-tssop 2.4 example this is an example part number: MC9S08PT16vld 3 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: table 1. parameter classifications p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. note the classification is shown in the column labeled c in the parameter tables where appropriate. ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 4 parameter classification MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 5
1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -6000 +6000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 4.4 voltage and current operating ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this document. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. symbol description min. max. unit v dd supply voltage C0.3 5.8 v i dd maximum current into v dd 120 ma table continues on the next page... ratings MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 6 freescale semiconductor, inc.
symbol description min. max. unit v dio digital input voltage (except reset, extal, and xtal) C0.3 v dd + 0.3 v v aio analog 1 , reset, extal, and xtal input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. general nonswitching electrical specifications 5.1.1 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 2. dc characteristics symbol c descriptions min typical 1 max unit operating voltage 2.7 5.5 v v oh p output high voltage all i/o pins, low-drive strength 5 v, i load = -2 ma v dd - 1.5 v c 3 v, i load = -0.6 ma v dd - 0.8 v p high current drive pins, high-drive strength 2 5 v, i load = -20 ma v dd - 1.5 v c 3 v, i load = -6 ma v dd - 0.8 v i oht d output high current max total i oh for all ports 5 v -100 ma 3 v -60 v ol p output low voltage all i/o pins, low-drive strength 5 v, i load = 2 ma 1.5 v c 3 v, i load = 0.6 ma 0.8 v p high current drive pins, high-drive strength 2 5 v, i load =20 ma 1.5 v c 3 v, i load = 6 ma 0.8 v i olt d output low current max total i ol for all ports 5 v 100 ma 3 v 60 table continues on the next page... 5 5.1 general MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 7
table 2. dc characteristics (continued) symbol c descriptions min typical 1 max unit v ih p input high voltage all digital inputs v dd >4.1v 0.70 v dd v v dd >2.7v 0.85 v dd v il p input low voltage all digital inputs v dd >4.1v 0.35 v dd v v dd >2.7v 0.30 v dd v hys c input hysteresis all digital inputs 0.06 v dd mv |i in | p input leakage current all input only pins (per pin) v in = v dd or v ss 0.1 1 a |i oz | p hi-z (off- state) leakage current all input/output (per pin) v in = v dd or v ss 0.1 1 a |i oztot | c total leakage combined for all inputs and hi-z pins all input only and i/o v in = v dd or v ss 2 a r pu p pullup resistors all digital inputs, when enabled (all i/o pins other than pta5/ irq/tclk/reset 17.5 52.5 k? r pu 3 p pullup resistors pta5/irq/tclk/ reset 17.5 52.5 k? i ic d dc injection current 4 , 5 , 6 single pin limit v in < v ss , v in > v dd -0.2 2 ma total mcu limit, includes sum of all stressed pins -5 25 c in c input capacitance, all pins 8 pf v ram c ram retention voltage 2.0 v 1. typical values are measured at 25 c. characterized, not tested. 2. only ptb4, ptb5, ptd0, ptd1 support ultra high current output. 3. the specified resistor value is the actual value internal to the device. the pullup value may appear higher when measured externally on the pin. 4. all functional non-supply pins, except for pta5, are internally clamped to v ss and v dd . 5. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 6. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is higher than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current higher than maximum injection current when the mcu is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). table 3. lvd and por specification symbol c description min typ max unit v por d por re-arm voltage 1 1.5 1.75 2.0 v v lvdh c falling low-voltage detect threshold - high range (lvdv = 1) 2 4.2 4.3 4.4 v table continues on the next page... nonswitching electrical specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 8 freescale semiconductor, inc.
table 3. lvd and por specification (continued) symbol c description min typ max unit v lvw1h c falling low- voltage warning threshold - high range level 1 falling (lvwv = 00) 4.3 4.4 4.5 v v lvw2h c level 2 falling (lvwv = 01) 4.5 4.5 4.6 v v lvw3h c level 3 falling (lvwv = 10) 4.6 4.6 4.7 v v lvw4h c level 4 falling (lvwv = 11) 4.7 4.7 4.8 v v hysh c high range low-voltage detect/warning hysteresis 100 mv v lvdl c falling low-voltage detect threshold - low range (lvdv = 0) 2.56 2.61 2.66 v v lvdw1l c falling low- voltage warning threshold - low range level 1 falling (lvwv = 00) 2.62 2.7 2.78 v v lvdw2l c level 2 falling (lvwv = 01) 2.72 2.8 2.88 v v lvdw3l c level 3 falling (lvwv = 10) 2.82 2.9 2.98 v v lvdw4l c level 4 falling (lvwv = 11) 2.92 3.0 3.08 v v hysdl c low range low-voltage detect hysteresis 40 mv v hyswl c low range low-voltage warning hysteresis 80 mv v bg p buffered bandgap output 3 1.14 1.16 1.18 v 1. maximum is highest voltage that por is guaranteed. 2. rising thresholds are falling threshold + hysteresis. 3. voltage factory trimmed at v dd = 5.0 v, temp = 25 c nonswitching electrical specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 9
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1 2 3 4 5 6 i oh (ma) v dd -v oh (v) v dd =3v v dd =5v figure 1. typical i oh vs. v dd -v oh 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5 10 15 20 25 i oh ( ma ) v dd - v oh (v) v dd =3v v dd =5v figure 2. typical i oh vs. v dd -v oh (high current drive) nonswitching electrical specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 10 freescale semiconductor, inc.
0 0.1 0.2 0.3 0.4 0.5 0.6 1 2 3 4 5 6 i ol ( ma ) v ol (v) v dd =3v v dd =5v figure 3. typical i ol vs. v ol 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 5 10 15 20 25 i ol (ma) v ol (v) v dd =3v v dd =5v figure 4. typical i ol vs. v ol (high current drive) nonswitching electrical specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 11
5.1.2 supply current characteristics this section includes information about power supply current in various operating modes. table 4. supply current characteristics num c parameter symbol bus freq v dd (v) typical 1 max unit temp 1 c run supply current fei mode, all modules on; run from flash ri dd 20 mhz 5 7.60 ma -40 to 105 c c 10 mhz 4.65 1 mhz 1.90 c 20 mhz 3 7.05 c 10 mhz 4.40 1 mhz 1.85 2 c run supply current fei mode, all modules off & gated; run from flash ri dd 20 mhz 5 5.88 ma -40 to 105 c c 10 mhz 3.70 1 mhz 1.85 c 20 mhz 3 5.35 c 10 mhz 3.42 1 mhz 1.80 3 p run supply current fbe mode, all modules on; run from ram ri dd 20 mhz 5 10.9 14.0 ma -40 to 105 c c 10 mhz 6.10 1 mhz 1.69 c 20 mhz 3 8.18 10 mhz 5.14 1 mhz 1.44 4 p run supply current fbe mode, all modules off & gated; run from ram ri dd 20 mhz 5 8.50 13.0 ma -40 to 105 c c 10 mhz 5.07 1 mhz 1.59 c 20 mhz 3 6.11 10 mhz 4.10 1 mhz 1.34 5 c wait mode current fei mode, all modules on wi dd 20 mhz 5 5.95 ma -40 to 105 c 10 mhz 3.50 1 mhz 1.24 c 20 mhz 3 5.45 10 mhz 3.25 1 mhz 1.20 6 c stop3 mode supply current no clocks active (except 1khz lpo clock) s3i dd 5 4.6 a -40 to 105 c c 3 4.5 -40 to 105 c table continues on the next page... nonswitching electrical specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 12 freescale semiconductor, inc.
table 4. supply current characteristics (continued) num c parameter symbol bus freq v dd (v) typical 1 max unit temp 7 c adc adder to stop3 adlpc = 1 adlsmp = 1 adco = 1 mode = 10b adiclk = 11b 5 40 a -40 to 105 c c 3 39 8 c tsi adder to stop3 2 ps = 010b nscn = 0x0f extchrg = 0 refchrg = 0 dvolt = 01b 5 121 a -40 to 105 c c 3 120 9 c lvd adder to stop3 3 5 128 a -40 to 105 c c 3 124 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. the current varies with tsi configuration and capacity of touch electrode. please refer to tsi electrical specifications . 3. lvd is periodically woken up from stop3 by 5% duty cycle. the period is equal to or less than 2 ms. 5.1.3 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation all play a significant role in emc performance. the system designer should consult freescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifically targeted at optimizing emc performance. switching specifications 5.2.1 control timing table 5. control timing num c rating symbol min typical 1 max unit 1 p bus frequency (t cyc = 1/f bus ) f bus dc 20 mhz 2 c internal low power oscillator frequency f lpo 1.0 khz table continues on the next page... 5.2 switching specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 13
table 5. control timing (continued) num c rating symbol min typical 1 max unit 3 d external reset pulse width 2 t extrst 1.5 t self_reset ns 4 d reset low drive t rstdrv 34 t cyc ns 5 d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ns 6 d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 t msh 100 ns 7 d irq pulse width asynchronous path 2 t ilih 100 ns d synchronous path 4 t ihil 1.5 t cyc ns 8 d keyboard interrupt pulse width asynchronous path 2 t ilih 100 ns d synchronous path t ihil 1.5 t cyc ns 9 c port rise and fall time - normal drive strength (hdrve_ptxx = 0) (load = 50 pf) 5 t rise 10.2 ns c t fall 9.5 ns c port rise and fall time - extreme high drive strength (hdrve_ptxx = 1) (load = 50 pf) 5 t rise 5.4 ns c t fall 4.6 ns 1. typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. 2. this is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. to enter bdm mode following a por, bkgd/ms must be held low during the powerup and for a hold time of t msh after v dd rises above v lvd . 4. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5. timing is shown with respect to 20% v dd and 80% v dd levels. temperature range -40 c to 105 c. ? ? ? ? ? ? ? ? t extrst reset pin figure 5. reset timing t ihil kbipx t ilih irq /kbipx figure 6. irq/kbipx timing switching specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 14 freescale semiconductor, inc.
5.2.2 debug trace timing specifications table 6. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns figure 7. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 8. trace data specifications 5.2.3 ftm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. table 7. ftm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0 f bus /4 hz table continues on the next page... switching specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 15
table 7. ftm input timing (continued) no. c function symbol min max unit 2 d external clock period t tclk 4 t cyc 3 d external clock high time t clkh 1.5 t cyc 4 d external clock low time t clkl 1.5 t cyc 5 d input capture pulse width t icpw 1.5 t cyc ? ? ? ? ? ? ? ? t tclk t clkh t clkl tclk figure 9. timer external clock ? ? ? ? ? ? ? ? t icpw ftmchn t icpw ftmchn figure 10. timer input capture pulse thermal specifications 5.3.1 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user- determined rather than being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. 5.3 thermal specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 16 freescale semiconductor, inc.
table 8. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h -40 to 105 c junction temperature range t j -40 to 150 c thermal resistance single-layer board 44-pin lqfp ja 76 c/w 32-pin lqfp ja 88 c/w 20-pin soic ja 82 c/w 20-pin tssop ja 116 c/w 16-pin tssop ja 130 c/w thermal resistance four-layer board 44-pin lqfp ja 54 c/w 32-pin lqfp ja 59 c/w 20-pin soic ja 54 c/w 20-pin tssop ja 76 c/w 16-pin tssop ja 87 c/w the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins - user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) solving the equations above for k gives: k = p d (t a + 273 c) + ja (p d ) 2 where k is a constant pertaining to the particular part. k can be determined by measuring p d (at equilibrium) for an known t a . using this value of k, the values of p d and t j can be obtained by solving the above equations iteratively for any value of t a . thermal specifications MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 17
6 peripheral operating requirements and behaviors 6.1 external oscillator (xosc) and ics characteristics table 9. xosc and ics specifications (temperature range = -40 to 105 c ambient) num c characteristic symbol min typical 1 max unit 1 c oscillator crystal or resonator low range (range = 0) f lo 32 40 khz c high range (range = 1) fee or fbe mode 2 f hi 4 20 mhz c high range (range = 1), high gain (hgo = 1), fbelp mode f hi 4 20 mhz c high range (range = 1), low power (hgo = 0), fbelp mode f hi 4 20 mhz 2 d load capacitors c1, c2 see note 3 3 d feedback resistor low frequency, low-power mode 4 r f m? low frequency, high-gain mode 10 m? high frequency, low- power mode 1 m? high frequency, high-gain mode 1 m? 4 d series resistor - low frequency low-power mode 4 r s k? high-gain mode 200 k? 5 d series resistor - high frequency low-power mode 4 r s k? d series resistor - high frequency, high-gain mode 4 mhz 0 k? d 8 mhz 0 k? d 16 mhz 0 k? 6 c crystal start-up time low range = 32.768 khz crystal; high range = 20 mhz crystal 5 , 6 low range, low power t cstl 1000 ms c low range, high power 800 ms c high range, low power t csth 3 ms c high range, high power 1.5 ms 7 t internal reference start-up time t irst 20 50 s 8 d square wave input clock frequency fee or fbe mode 2 f extal 0.03125 5 mhz d fbelp mode 0 20 mhz 9 p average internal reference frequency - trimmed f int_t 32.768 khz 10 p dco output frequency range - trimmed f dco_t 16 20 mhz table continues on the next page... peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 18 freescale semiconductor, inc.
table 9. xosc and ics specifications (temperature range = -40 to 105 c ambient) (continued) num c characteristic symbol min typical 1 max unit 11 p total deviation of dco output from trimmed frequency 5 over full voltage and temperature range f dco_t 2.0 %f dco c over fixed voltage and temperature range of 0 to 70 c 1.0 12 c fll acquisition time 5 , 7 t acquire 2 ms 13 c long term jitter of dco output clock (averaged over 2 ms interval) 8 c jitter 0.02 0.2 %f dco 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. when ics is configured for fee or fbe mode, input clock source must be divisible using rdiv to within the range of 31.25 khz to 39.0625 khz. 3. see crystal or resonator manufacturer's recommendation. 4. load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated internally when range = hgo = 0. 5. this parameter is characterized and not tested on each device. 6. proper pc board layout procedures must be followed to achieve specifications. 7. this specification applies to any time the fll reference source or reference divider is changed, trim value changed, dmx32 bit is changed, drs bit is changed, or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. xosc extal xtal crystal or resonator r s c 2 r f c 1 figure 11. typical crystal or resonator circuit peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 19
6.2 nvm specifications this section provides details about program/erase times and program-erase endurance for the flash and eeprom memories. table 10. flash characteristics c characteristic symbol min 1 typical 2 max 3 unit 4 d supply voltage for program/erase -40 c to 105 c v prog/erase 2.7 5.5 v d supply voltage for read operation v read 2.7 5.5 v d nvm bus frequency f nvmbus 1 25 mhz d nvm operating frequency f nvmop 0.8 1.05 mhz d erase verify all blocks t vfyall 17030 t cyc d erase verify flash block t rd1blk 16977 t cyc d erase verify eeprom block t rd1blk 843 t cyc d erase verify flash section t rd1sec 517 t cyc d erase verify eeprom section t drd1sec 0.10 0.10 0.11 ms d read once t rdonce 455 t cyc d program flash (2 word) t pgm2 0.12 0.12 0.14 ms d program flash (4 word) t pgm4 0.20 0.21 0.24 ms d program once t pgmonce 0.20 0.21 0.24 ms d program eeprom (1 byte) t dpgm1 0.02 0.02 0.02 ms d program eeprom (2 byte) t dpgm2 0.17 0.18 0.20 ms d erase all blocks t ersall 96.01 100.78 125.80 ms d erase flash block t ersblk 95.98 100.75 125.76 ms d erase flash sector t erspg 19.10 20.05 25.05 ms d erase eeprom sector t derspg 4.81 5.05 6.30 ms d unsecure flash t unsecu 96.01 100.78 125.80 ms d verify backdoor access key t vfykey 469 t cyc d set user margin level t mloadu 442 t cyc c flash program/erase endurance t l to t h = -40 c to 105 c n flpe 10 k 100 k cycles c eeprom program/erase endurance tl to th = -40 c to 105 c n flpe 50 k 500 k cycles c data retention at an average junction temperature of t javg = 85c after up to 10,000 program/erase cycles t d_ret 15 100 years 1. minimun times are based on maxmum f nvmop and maximum f nvmbus 2. typical times are based on typical f nvmop and maximum f nvmbus 3. maximum times are based on minimum f nvmop and maximum f nvmbus 4. t cyc = 1 / f nvmbus program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the memory section. peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 20 freescale semiconductor, inc.
6.3 analog 6.3.1 adc characteristics table 11. 5 v 12-bit adc operating conditions characteri stic conditions symb min typ 1 max unit comment supply voltage absolute v dda 2.7 5.5 v delta to v dd (v dd -v ddad ) v dda -100 0 +100 mv ground voltage delta to v ss (v ss -v ssa ) 2 v ssa -100 0 +100 mv input voltage v adin v refl v refh v input capacitance c adin 4.5 5.5 pf input resistance r adin 3 5 k? analog source resistance 12-bit mode ? f adck > 4 mhz ? f adck < 4 mhz r as 2 5 k? external to mcu 10-bit mode ? f adck > 4 mhz ? f adck < 4 mhz 5 10 8-bit mode (all valid f adck ) 10 adc conversion clock frequency high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0 1. typical values assume v dda = 5.0 v, temp = 25c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 21
adc sar engine simplified channel select circuit simplified input pin equivalent circuit pad leakage due to input protection z as r as c as v adin v as z adin r adin r adin r adin r adin input pin input pin input pin c adin figure 12. adc input impedance equivalency diagram table 12. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) characteristic conditions c symb min typ 1 max unit supply current adlpc = 1 adlsmp = 1 adco = 1 t i dda 133 a supply current adlpc = 1 adlsmp = 0 adco = 1 t i dda 218 a supply current adlpc = 0 adlsmp = 1 adco = 1 t i dda 327 a supply current adlpc = 0 adlsmp = 0 adco = 1 t i ddad 582 990 a supply current stop, reset, module off t i dda 0.011 1 a table continues on the next page... peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 22 freescale semiconductor, inc.
table 12. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) characteristic conditions c symb min typ 1 max unit adc asynchronous clock source high speed (adlpc = 0) p f adack 2 3.3 5 mhz low power (adlpc = 1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp = 0) t t adc 20 adck cycles long sample (adlsmp = 1) 40 sample time short sample (adlsmp = 0) t t ads 3.5 adck cycles long sample (adlsmp = 1) 23.5 total unadjusted error 2 12-bit mode t e tue 5.0 lsb 3 10-bit mode p 1.5 2.0 8-bit mode p 0.7 1.0 differential non- liniarity 12-bit mode t dnl 1.0 lsb 3 10-bit mode 4 p 0.25 0.5 8-bit mode 4 p 0.15 0.25 integral non-linearity 12-bit mode t inl 1.0 lsb 3 10-bit mode t 0.3 0.5 8-bit mode t 0.15 0.25 zero-scale error 5 12-bit mode c e zs 2.0 lsb 3 10-bit mode p 0.25 1.0 8-bit mode p 0.65 1.0 full-scale error 6 12-bit mode t e fs 2.5 lsb 3 10-bit mode t 0.5 1.0 8-bit mode t 0.5 1.0 quantization error 12 bit modes d e q 0.5 lsb 3 input leakage error 7 all modes d e il i in * r as mv temp sensor slope -40cC 25c d m 3.266 mv/c 25cC 125c 3.638 temp sensor voltage 25c d v temp25 1.396 v 1. typical values assume v dda = 5.0 v, temp = 25c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. includes quantization 3. 1 lsb = (v refh - v refl )/2 n 4. monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 5. v adin = v ssa 6. v adin = v dda 7. i in = leakage current (refer to dc characteristics) peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 23
6.3.2 analog comparator (acmp) electricals table 13. comparator electrical specifications c characteristic symbol min typical max unit d supply voltage v dda 2.7 5.5 v t supply current (operation mode) i dda 10 20 a d analog input voltage v ain v ss - 0.3 v dda v p analog input offset voltage v aio 40 mv c analog comparator hysteresis (hyst=0) v h 15 20 mv c analog comparator hysteresis (hyst=1) v h 20 30 mv t supply current (off mode) i ddaoff 60 na c propagation delay t d 0.4 1 s 6.4 communication interfaces 6.4.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. refer to the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 70% v dd , unless noted, and 100 pf load on all spi pins. all timing assumes slew rate control is disabled and high drive strength is enabled for spi output pins. table 14. spi master mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation f bus /2048 f bus /2 hz f bus is the bus clock 2 t spsck spsck period 2 x t bus 2048 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t bus - 30 1024 x t bus ns 6 t su data setup time (inputs) 15 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 25 ns 9 t ho data hold time (outputs) 0 ns table continues on the next page... peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 24 freescale semiconductor, inc.
table 14. spi master mode timing (continued) nu m. symbol description min. max. unit comment 10 t ri rise time input t bus - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output (output) (output) miso (input) mosi (output) ss 1 (output) 2 8 6 7 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 9 5 5 3 (cpol 0) (cpol 1) 4 11 11 10 10 spsck spsck = = 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. figure 13. spi master mode timing (cpha=0) <> <> 38 (output) (output) miso (input) mosi (output) 2 6 7 msb in 2 bit 6 . . . 1 lsb in master msb out master lsb out bit 6 . . . 1 5 5 8 10 11 port data (cpol 0) (cpol 1) port data ss 1 (output) 3 10 11 4 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 2 9 spsck spsck = = figure 14. spi master mode timing (cpha=1) peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 25
table 15. spi slave mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation 0 f bus /4 hz f bus is the bus clock as defined in . 2 t spsck spsck period 4 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1 t bus 4 t lag enable lag time 1 t bus 5 t wspsck clock (spsck) high or low time t bus - 30 ns 6 t su data setup time (inputs) 15 ns 7 t hi data hold time (inputs) 25 ns 8 t a slave access time t bus ns time to data active from high-impedance state 9 t dis slave miso disable time t bus ns hold time to high- impedance state 10 t v data valid (after spsck edge) 25 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t bus - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output (input) (input) mosi (input) miso (output) ss (input) 2 10 6 7 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 5 5 3 8 (cpol 0) (cpol 1) 4 13 note: not defined! 12 12 11 see 13 note 9 see note spsck spsck = = figure 15. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 26 freescale semiconductor, inc.
(input) (input) mosi (input) miso (output) 2 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 5 5 10 12 13 11 (cpol 0) (cpol 1) ss (input) 3 12 13 4 note: not defined! slave 8 9 see note spsck spsck = = figure 16. spi slave mode timing (cpha=1) 6.5 human-machine interfaces (hmi) 6.5.1 tsi electrical specifications table 16. tsi electrical specifications symbol description min. type max unit tsi_runf fixed power consumption in run mode 100 a tsi_runv variable power consumption in run mode (depends on oscillator's current selection) 1.0 128 a tsi_en power consumption in enable mode 100 a tsi_dis power consumption in disable mode 1.2 a tsi_ten tsi analog enable time 66 s tsi_cref tsi reference capacitor 1.0 pf tsi_dvolt voltage variation of vp & vm around nominal values -10 10 % dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. 7 dimensions MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 27
to find a package drawing, go to www.freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 16-pin tssop 98ash70247a 20-pin soic 98asb42343b 20-pin tssop 98ash70169a 32-pin lqfp 98ash70029a 44-pin lqfp 98ass23225w pinout 8.1 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. table 17. pin availability by package pin-count pin number lowest priority <-- --> highest 44-lqfp 32-lqfp 20-tssop 16-tssop port pin alt 1 alt 2 alt 3 alt 4 1 1 ptd1 1 ftm2ch3 2 2 ptd0 1 ftm2ch2 3 pte4 tclk2 4 pte3 busout 5 3 3 3 v dd 6 4 v dda v refh 7 5 v ssa v refl 8 6 4 4 v ss 9 7 5 5 ptb7 scl extal 10 8 6 6 ptb6 sda xtal 11 vss 12 9 7 7 ptb5 1 ftm2ch5 ss0 13 10 8 8 ptb4 1 ftm2ch4 miso0 14 11 9 ptc3 ftm2ch3 adp11 tsi9 15 12 10 ptc2 ftm2ch2 adp10 tsi8 16 ptd7 17 ptd6 table continues on the next page... 8 pinout MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 28 freescale semiconductor, inc.
table 17. pin availability by package pin-count (continued) pin number lowest priority <-- --> highest 44-lqfp 32-lqfp 20-tssop 16-tssop port pin alt 1 alt 2 alt 3 alt 4 18 ptd5 19 13 11 ptc1 ftm2ch1 adp9 tsi7 20 14 12 ptc0 ftm2ch0 adp8 tsi6 21 15 13 9 ptb3 kbi0p7 mosi0 adp7 tsi5 22 16 14 10 ptb2 kbi0p6 spsck0 adp6 tsi4 23 17 15 11 ptb1 kbi0p5 txd0 adp5 tsi3 24 18 16 12 ptb0 kbi0p4 rxd0 adp4 tsi2 25 19 pta7 ftm2fault2 adp3 tsi1 26 20 pta6 ftm2fault1 adp2 tsi0 27 vss 28 v dd 29 ptd4 30 21 ptd3 tsi15 31 22 ptd2 tsi14 32 23 17 13 pta3 2 kbi0p3 txd0 scl 33 24 18 14 pta2 2 kbi0p2 rxd0 sda 34 25 19 15 pta1 kbi0p1 ftm0ch1 acmp1 adp1 35 26 20 16 pta0 kbi0p0 ftm0ch0 acmp0 adp0 36 27 ptc7 txd1 tsi13 37 28 ptc6 rxd1 tsi12 38 pte2 miso0 39 pte1 mosi0 40 pte0 spsck0 41 29 ptc5 ftm0ch1 tsi11 42 30 ptc4 ftm0ch0 tsi10 43 31 1 1 pta5 irq tclk0 reset 44 32 2 2 pta4 acmpo bkgd ms 1. this is a high current drive pin when operated as output. 2. this is a true open-drain pin when operated as output. note when an alternative function is first enabled, it is possible to get a spurious edge to the module. user software must clear any associated flags before interrupts are enabled. the table above illustrates the priority if multiple modules are enabled. the highest priority module will have control over the pin. selecting a higher priority pin function with a lower priority function pinout MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 29
already enabled can cause spurious edges to the lower priority module. disable all modules that share a pin before enabling another module. 8.2 device pin assignment 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 ptd1/ftm2ch3 1 ptd0/ftm2ch2 1 pte4/tclk2 pte3/busout v dd v dda /v refh v ssa /v refl v ss ptb7/scl/extal ptb6/sda/xtal v ss ptb5/ftm2ch5/ss0 1 ptb4/ftm2ch4/miso0 1 ptc3/ftm2ch3/adp11/tsi9 ptc2/ftm2ch2/adp10/tsi8 ptd7 ptd6 ptd5 ptc1/ftm2ch1/adp9/tsi7 ptc0/ftm2ch0/adp8/tsi6 2 2 ptd4 ptd2/tsi14 ptd3/tsi15 v dd v ss pta4/acmpo/bkgd/ms ptc4/ftm0ch0/tsi10 ptc5/ftm0ch1/tsi11 pte0/spsck0 pte1/mosi0 pte2/miso0 1. high source/sink current pins 2. true open drain pins ptb2/kbi0p6/spsck0/adp6/tsi4 ptb3/kbi0p7/mosi0/adp7/tsi5 pta3/kbi0p3/txd0/scl pta2/kbi0p2/rxd0/sda pta5/irq/tclk0/reset pta6/ftm2fault1/adp2/tsi0 pta7/ftm2fault2/adp3/tsi1 ptb0/kbi0p4/rxd0/adp4/tsi2 ptb1/kbi0p5/txd0/adp5/tsi3 pta1/kbi0p1/ftm0ch1/acmp1/adp1 pta0/kbi0p0/ftm0ch0/acmp0/adp0 ptc7/txd1/tsi13 ptc6/rxd1/tsi12 pins in bold figure 17. MC9S08PT16 44-pin lqfp package pinout MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 30 freescale semiconductor, inc. are not available on less pin-count packages.
ptd1/ftm2ch3 ptd0/ftm2ch2 v dd v dda /v refh v ssa /v refl v ss ptb7/scl/extal ptb6/sda/xtal ptb5/ftm2ch5/ss0 1 ptb4/ftm2ch4/miso0 1 ptc1/ftm2ch1/adp9/tsi7 ptc0/ftm2ch0/adp8/tsi6 pta2/kbi0p2/rxd0/sda 2 pta3/kbi0p3/txd0/scl 2 ptd2/tsi14 ptd3/tsi15 pta6/ftm2fault1/adp2/tsi0 pta7/ftm2fault2/adp3/tsi1 ptb0/kbi0p4/rxd0/adp4/tsi2 ptc4/ftm0ch0/tsi10 ptc5/ftm0ch1/tsi11 ptc6/rxd1/tsi12 ptc7/txd1/tsi13 ptb1/kbi0p5/txd0/adp5/tsi3 pta4/acmpo/bkgd/ms pta5/irq/tclk0/reset pta0/kbi0p0/ftm0ch0/acmp0/adp0 pta1/kbi0p1/ftm0ch1/acmp1/adp1 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 bold 1. high source/sink current pins 2. true open drain pins ptc3/ftm2ch3/adp11/tsi9 ptc2/ftm2ch2/adp10/tsi8 ptb3/kbi0p7/mosi0/adp7/tsi5 ptb2/kbi0p6/spsck0/adp6/tsi4 1 1 pins in are not available on less pin-count packages. figure 18. MC9S08PT16 32-pin lqfp package 20 19 18 17 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 v dd v ss ptb7/scl/extal ptb6/sda/xtal 1 ptb4/ftm2ch4/miso0 1 ptc1/ftm2ch1/adp9/tsi7 ptc0/ftm2ch0/adp8/tsi6 ptb3/kbi0p7/mosi0/adp7/tsi5 ptb2/kbi0p6/spsck0/adp6/tsi4 pta2/kbi0p2/rxd0/sda 2 pta3/kbi0p3/txd0/scl 2 ptb0/kbi0p4/rxd0/adp4/tsi2 ptb1/kbi0p5/txd0/adp5/tsi3 pta4/acmpo/bkgd/ms pta0/kbi0p0/ftm0ch0/acmp0/adp0 pta1/kbi0p1/ftm0ch1/acmp1/adp1 bold are not available on less pin-count packages. 1. high source/sink current pins 2. true open drain pins pins in pta5/irq/tclk0/reset ptb5/ftm2ch5/ss0 ptc3/ftm2ch3/adp11/tsi9 ptc2/ftm2ch2/adp10/tsi8 figure 19. MC9S08PT16 20-pin soic and tssop package pinout MC9S08PT16 series data sheet, rev. 1, 7/4/2012. freescale semiconductor, inc. 31
9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 v dd v ss ptb7/scl/extal ptb6/sda/xtal 1 ptb4/ftm2ch4/miso0 1 ptb3/kbi0p7/mosi0/adp7/tsi5 ptb2/kbi0p6/spsck0/adp6/tsi4 pta2/kbi0p2/rxd0/sda 2 pta3/kbi0p3/txd0/scl 2 ptb0/kbi0p4/rxd0/adp4/tsi2 ptb1/kbi0p5/txd0/adp5/tsi3 pta4/acmpo/bkgd/ms pta0/kbi0p0/ftm0ch0/acmp0/adp0 pta1/kbi0p1/ftm0ch1/acmp1/adp1 bold are not available on less pin-count packages. 1. high source/sink current pins 2. true open drain pins pins in pta5/irq/tclk0/reset ptb5/ftm2ch5/ss0 figure 20. MC9S08PT16 16-pin tssop package 9 revision history the following table provides a revision history for this document. table 18. revision history rev. no. date substantial changes 1 7/2012 initial public release revision history MC9S08PT16 series data sheet, rev. 1, 7/4/2012. 32 freescale semiconductor, inc.
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com document number: MC9S08PT16 rev. 1, 7/4/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2011C2012 freescale semiconductor, inc.

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